PIC18F45J11-I/ML【PDF 10/228 页】IC PIC MCU FLASH 32K 2V 44-QFN

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录3862

6页 7页 8页 9页 [10页]11页 12页 13页 14页

2010 Microchip Technology Inc.

DS70138G-page 107

dsPIC30F3014/4013

16.5.2

FRAMING ERROR (FERR)

The FERR bit (UxSTA<2>) is set if a ‘0’ is detected

instead of a Stop bit. If two Stop bits are selected, both

Stop bits must be ‘1’; otherwise, FERR is set. The read-

only FERR bit is buffered along with the received data;

it is cleared on any Reset.

16.5.3

PARITY ERROR (PERR)

The PERR bit (UxSTA<3>) is set if the parity of the

received word is incorrect. This error bit is applicable

only if a Parity mode (odd or even) is selected. The

read-only PERR bit is buffered along with the received

data bytes; it is cleared on any Reset.

16.5.4

IDLE STATUS

When the receiver is active (i.e., between the initial

detection of the Start bit and the completion of the Stop

bit), the RIDLE bit (UxSTA<4>) is ‘0’. Between the com-

pletion of the Stop bit and detection of the next Start bit,

the RIDLE bit is ‘1’, indicating that the UART is Idle.

16.5.5

RECEIVE BREAK

The receiver counts and expects a certain number of bit

times based on the values programmed in the PDSEL

(UxMODE<2:1>) and STSEL (UxMODE<0>) bits.

If the break is longer than 13 bit times, the reception is

considered complete after the number of bit times

specified by PDSEL and STSEL. The URXDA bit is set,

FERR is set, zeros are loaded into the receive FIFO,

interrupts are generated if appropriate, and the RIDLE

bit is set.

When the module receives a long Break signal and the

receiver has detected the Start bit, the data bits and the

invalid Stop bit (which sets the FERR), the receiver

must wait for a valid Stop bit before looking for the next

Start bit. It cannot assume that the Break condition on

the line is the next Start bit.

Break is regarded as a character containing all ‘0’s with

the FERR bit set. The Break character is loaded into

the buffer. No further reception can occur until a Stop bit

is received. Note that RIDLE goes high when the Stop

bit has not yet been received.

16.6

Address Detect Mode

Setting the ADDEN bit (UxSTA<5>) enables this

special mode in which a 9th bit (URX8) value of ‘1’

identifies the received word as an address, rather than

data. This mode is only applicable for 9-bit data

communication. The URXISEL control bit does not

have any impact on interrupt generation in this mode

since an interrupt (if enabled) is generated every time

the received word has the 9th bit set.

16.7

Loopback Mode

Setting the LPBACK bit enables this special mode in

which the UxTX pin is internally connected to the UxRX

pin. When configured for the Loopback mode, the

UxRX pin is disconnected from the internal UART

receive logic. However, the UxTX pin still functions as

in a normal operation.

To select this mode:

Configure UART for desired mode of operation.

Set LPBACK = 1 to enable Loopback mode.

Enable transmission as defined in Section 16.3

“Transmitting Data”.

16.8

Baud Rate Generator

The UART has a 16-bit Baud Rate Generator to allow

maximum flexibility in baud rate generation. The Baud

Rate Generator register (UxBRG) is readable and

writable. The baud rate is computed as follows:

BRG = 16-bit value held in UxBRG register

(0 through 65535)

FCY = Instruction Clock Rate (1/TCY)

The Baud Rate is given by Equation 16-1.

EQUATION 16-1:

BAUD RATE

Therefore, the maximum baud rate possible is:

FCY/16 (if BRG = 0),

and the minimum baud rate possible is:

FCY/(16 * 65536).

With a full 16-bit Baud Rate Generator at 30 MIPS

operation, the minimum baud rate achievable is

28.5 bps.

Baud Rate = FCY/(16*(BRG+1))

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式